1. Field of the Invention
The present invention relates to a semiconductor fabrication process. More particularly, the present invention relates to an improved lithography method for shrinking the critical dimension (CD) of semiconductor devices to a scale that exceeds the limit of the wavelength of exposing light, and, at the same time, improving the CD-shrinkage uniformity.
2. Description of the Prior Art
Each year, chip manufacturers bring out the next great computer chip that boosts computing power and allows our personal computers to do more than we imagined just a decade ago. As of 2001, microchips being made with deep-ultraviolet (DUV) lithography are made with 248-nanometer light. As of 2001, some manufacturers are transitioning over to using 193-nanometer light. It is believed that DUV lithography will reach its limits around 2004 and 2005, which means that Moore""s law would also come to an end.
As known in the art, the smallest circuit that can be created by DUV lithography is 100 nanometers due to its wavelength limit. Since cutting edge nano-scale pattern transfer technologies such as electron beam lithography are costly (or not mature enough) for the chip manufacturers, some approaches have been addressed to elongate the life of the DUV lithography, which can fabricate resist patterns having a critical dimension that exceeds the limit of the wavelength of exposing light. However, none of the prior art CD shrinking methods could provide good CD-shrinkage uniformity.
In 1998, by way of example, Toyoshima et al. disclosed an improved KrF lithography method (xe2x80x9c0.1 xcexcm Level Contact Hole Pattern Formation with KrF Lithography by Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS),xe2x80x9d T. Toyoshima, et al., Advanced Technology RandD Center, Mitsubishi Electric Corp., IEDM IEEE 1998, pp. 98-333-336), in which, with reference to FIG. 1, a first resist pattern, which is capable of generating an acid, is formed on a semiconductor device layer (Step 1). Over the first resist pattern, a layer of a second resist, which is capable of undergoing a cross-linking reaction in the presence of an acid, is formed (Step 2). Then, a cross-linked film is formed in portions of the layer of the second resist at the boundary with the first resist by action of an acid from the first resist (Step 3). Thereafter, non-cross-linked portions of the second resist are removed to form a finely isolated resist pattern (Step 4). The semiconductor device layer is etched, via a mask of the finely isolated resist pattern, to form fine holes (Step 5).
It is therefore a primary object of the claimed invention to provide a method for fabricating semiconductor devices having a shrunk critical dimension and improved CD-shrinkage uniformity.
According to the claimed invention, a method for shrinking critical dimension of semiconductor devices comprises forming a first pattern of a photoresist layer on a semiconductor device layer, wherein the photoresist layer has been developed and exposes portions of the underlying semiconductor device layer, followed by performing a blanket exposing process to expose the photoresist layer and the exposed semiconductor device layer thereof to light having a wavelength capable of being absorbed by the photoresist layer to provide the photoresist layer with a predetermined energy per unit area, thereby producing photo generated acids therein. A first thermal process is then performed to diffuse the photo generated acids formed within the photoresist layer and to equalize glass transition temperature (Tg) of the photoresist layer. A second thermal process is thereafter carried out. The first thermal process is carried out under a temperature lower than the glass transition temperature (Tg) of the photoresist layer.
Other objects and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.